Alif Semiconductor /AE512F80F5582AS_CM55_HP_View /GPU2D /GPU2D_IRQCTL

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Interpret as GPU2D_IRQCTL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Val_0x0)D2IRQCTL_ENABLE_FINISH_ENUM 0 (Val_0x0)D2IRQCTL_ENABLE_FINISH_DLIST 0 (Val_0x0)D2IRQCTL_CLR_FINISH_ENUM 0 (Val_0x0)D2IRQCTL_CLR_FINISH_DLIST 0 (Val_0x0)D2IRQCTL_ENABLE_BUS_ERROR 0 (Val_0x0)D2IRQCTL_CLR_BUS_ERROR

D2IRQCTL_ENABLE_BUS_ERROR=Val_0x0, D2IRQCTL_CLR_BUS_ERROR=Val_0x0, D2IRQCTL_ENABLE_FINISH_DLIST=Val_0x0, D2IRQCTL_CLR_FINISH_DLIST=Val_0x0, D2IRQCTL_CLR_FINISH_ENUM=Val_0x0, D2IRQCTL_ENABLE_FINISH_ENUM=Val_0x0

Description

Interrupt Control Register

Fields

D2IRQCTL_ENABLE_FINISH_ENUM

0 (Val_0x0): Disable enumeration finished interrupt

1 (Val_0x1): Enable enumeration finished interrupt

D2IRQCTL_ENABLE_FINISH_DLIST

0 (Val_0x0): Disable display list finished interrupt

1 (Val_0x1): Enable display list finished interrupt

D2IRQCTL_CLR_FINISH_ENUM

0 (Val_0x0): Leave enumeration interrupt untouched

1 (Val_0x1): Clear enumeration interrupt

D2IRQCTL_CLR_FINISH_DLIST

0 (Val_0x0): Leave display list interrupt untouched

1 (Val_0x1): Clear display list interrupt

D2IRQCTL_ENABLE_BUS_ERROR

0 (Val_0x0): Disable bus error interrupt

1 (Val_0x1): Enable bus error interrupt

D2IRQCTL_CLR_BUS_ERROR

0 (Val_0x0): Leave bus error interrupt untouched

1 (Val_0x1): Clear bus error interrupt

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